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　　1.HJX-AD9371-SDR  System Block： 

　　5. Digital signal processing unit: adopts Xilinx's new-generation Artix-7 series FPGA, which has rich DSP and Logic resources, and is compatible with 7A100T / 7A200T at the same time, which is convenient for customers to choose according to specific project conditions. Relevant variable parameters (including the function selection of each module in the FPGA, peripheral DSA chip attenuation, AD9371 chip frequency, etc.) can be directly modified on the host computer through the serial port. The following is the FPGA framework when receiving a data rate of 122.88M and transmitting a data rate of 245.76M. When sending and receiving the same data rate, no up-conversion module (Up2) is required. The DATACAPTURE module can choose to capture data of a certain depth from RX / TX / ORX and transmit it to the upper computer through ARM, which is convenient for users to do spectrum analysis directly on matlab. The MUX module can select the signal source output from the transmitting end, including the DDS single tone output, the RX end signal, and the ORX end signal of the FPGA.

　　4.Test Results

 　　The following are LO and image suppression indicators and TDD-LTEEVM tests (please contact us for more detailed test content)

(1).LO and Image reject performance

 　　Test conditions: single-tone signal mode, the input power of the signal source is -14dBm, and the power output to the spectrum analyzer after the HJX-AD9371-SDR development board is -5dBm.

(2).EVM performance

- Microwave non-line-of-sight (NLOS) return trip system

- 5 G prototype